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generalplus technology inc. reserves the right to change this documentation without prior notice. information provided by gene ralplus technology inc. is believed to be accurate and reliable. however, generalplus technology inc. makes no warranty for any errors which may appear in this document. contact generalplus technology inc. to obtain the latest version of device specifications before plac ing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other rights of third parties which may result from its use. g g p p l l 1 1 0 0 b b 7kb lcd controller/driver may 29, 2014 version 1.5 in addition, generalplus products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the expre ss written approval of generalplus.
gpl10b ? generalplus technology inc. proprietary & confidential 2 may 29, 2014 version: 1.5 table of contents page 7kb lcd c ontroller /d river ......................................................................................................................................................................... 1 t able of c ontents .......................................................................................................................................................................................... 2 7kb lcd controller/driver ................................................................................................................................................................... 3 1. general description .......................................................................................................................................................................... 3 2. block diagram ...................................................................................................................................................................................... 3 3. features .................................................................................................................................................................................................. 3 4. signal descriptions ............................................................................................................................................................................ 4 4.1. pad a ssignment ................................................................................................................................................................................. 4 5. functional descriptions.................................................................................................................................................................. 5 5.1. rom .................................................................................................................................................................................................... 5 5.2. ram ..................................................................................................................................................................................................... 5 5.3. m emory and i/o m ap ........................................................................................................................................................................... 5 5.4. o scillators ........................................................................................................................................................................................ 5 5.5. s top c lock m ode ............................................................................................................................................................................... 6 5.6. t imer /c ounter ................................................................................................................................................................................... 6 5.7. i nterrupts .......................................................................................................................................................................................... 6 5.8. t one o utput ....................................................................................................................................................................................... 6 5.9. l iquid c rystal d isplay ....................................................................................................................................................................... 6 5.10. o utput w aveform of the lcd d river .............................................................................................................................................. 7 5.11. r eset f unction ................................................................................................................................................................................ 13 5.12. w atchdog f unction ......................................................................................................................................................................... 13 5.13. m ask o ption ..................................................................................................................................................................................... 13 6. i/o port configuration .................................................................................................................................................................... 14 6.1. i nput ioef p ort : ioef0 to ioef5.................................................................................................................................................... 14 6.2. i nput /o utput iocd p ort : iocd0 to iocd3 .................................................................................................................................... 14 7. electrical specifications ............................................................................................................................................................. 15 7.1. a bsolute m aximum r atings ............................................................................................................................................................. 15 7.2. dc c haracteristics (vdd = 3.0v, t a = 25 ) .................................................................................................................................. 15 7.3. dc c haracteristics (vdd = 4.5v, t a = 25 ) .................................................................................................................................. 15 7.4. t he r elationships between the r osc and the f osc ......................................................................................................................... 16 7.5. t he r elationships between the f osc and the vdd ........................................................................................................................ 16 7.6. t he r elationships between the f cpu and the i op ............................................................................................................................ 16 7.7. t he r elationships between the r osc32k and the f 32k ...................................................................................................................... 16 7.8. t he r elationships between the f 32k and the vdd ......................................................................................................................... 17 7.9. ac c haracteristics ......................................................................................................................................................................... 17 8. application circuits ......................................................................................................................................................................... 18 8.1. gpl10b a pplication c ircuit ............................................................................................................................................................ 18 8.2. a udio d river ..................................................................................................................................................................................... 19 9. package/pad locations ................................................................................................................................................................... 20 9.1. o rdering i nformation ..................................................................................................................................................................... 20 9.2. p ackage i nformation ....................................................................................................................................................................... 21 10. disclaimer ............................................................................................................................................................................................. 22 11. revision history ................................................................................................................................................................................. 23
gpl10b ? generalplus technology inc. proprietary & confidential 3 may 29, 2014 version: 1.5 7kb lcd controller/driver 1. general description the gpl10b is a cmos 8-bit si ngle chip micro-controller which contains lcd drivers, rom, sr am, i/o, timer/counter and tone output for directly driving buzzer on a single chip. the gpl10b is designed to drive lcd directly and performs efficient controller function as well as arithmetic function. with the on chip crystal oscillator, the real time clo ck can be easily implemented. for power saving, a software controllable standby switch is also built-in. the gpl10b is widely used in el ectronic products requiring very low power consumption, e.g. multi-function watch, calendar, calculator, and thermometer or lcd game with audio output. 2. block diagram 8-bit risc processor rosc gen time base & interrupt logic 7k x 8 rom 96 x 8 sram one 12-bit auto reload timer 10 i/o p o r t tone 32 segments x 4 commands lcd driver ioef5 - 0 (i) iocd3 - 0 (i/o) seg31 - 0 com3 - 0 rosc x32i x32o 3. features ? built-in 8-bit cpu ? operating voltage: 2.0v to 5.5v ? max. cpu clock: 2.0mhz @ 2.0v ? rom capacity: 7k x 8 bits ? ram capacity: 96 x 8 bits ? direct driver for lcd: 4 commons x 32 segments (1/2, 1/3 bias, 1/2, 1/3, 1/4 duty) ? input port: six input pins with key wakeup function with four different configurations (mask option) ? i/o port: four special purpose i/o for implement thermometer ? timer/counter: one 12-bit timer/counter ? six interrupt sources: . external interrupt . timer interrupt . 2khz interrupt . lcd service interrupt (in lcd share mode) . 128hz interrupt . 2hz interrupt ? dual clock system: one built-in rc oscillator that selects internal or external resistor (m ask option) for cpu. the other built-in crystal oscillator or rc oscillator (mask option) for lcd scanning. ? tone output: tone output for directly driving buzzer ? system reset: external reset, watchdog reset and low voltage reset (2.0v) are built-in ? low operating current: typical current < 8ua @ 3.0v for timepiece products
gpl10b ? generalplus technology inc. proprietary & confidential 4 may 29, 2014 version: 1.5 4. signal descriptions mnemonic pin no. type description seg31 - 0 5 - 36 o lcd driver segment output com3 - 0 37- 40 o lcd driver common output ioef5 - 2 ioef1 - 0 4 - 1 54 - 53 i input port (also for key wake-up input) iocd3 - 0 49 - 46 i/o i/o port rosc 51 i r-osc input, connect to vdd through a resistor reset 50 i external reset input aud 42 o tone output x32i 45 i 32.768khz crystal input/r oscillator input x32o 44 o 32.768khz crystal output test 52 i test input vdd 43 i power input vss 41 i ground input 4.1. pad assignment this ic substrate should be connected to vss note1: to ensure that the ic functions properly, please bond all of vdd and vss pins. note2: the 0.1uf capacitor between vdd and vss should be placed to ic as close as possible.
gpl10b ? generalplus technology inc. proprietary & confidential 5 may 29, 2014 version: 1.5 5. functional descriptions 5.1. rom the gpl10b provides 7.5k bytes rom size of which 7k bytes for program and data. the other 0.5k bytes are for generalplus internal test use, ranged from $0200 to $1fff. 5.2. ram the gpl10b provides 96 bytes ram. the ram is for both stack and data storage, ranged from $00a0 to $00ff. 5.3. memory and i/o map $0000 $001f $00a0 $00ff $0100 $01ff $0200 $03ff $0400 $1fff generalplus test program $05ff $0600 h/w register,i/os user ram and stack dummy for ice debug user's program data area rom user's program data area rom 5.4. oscillators the gpl10b is a dual clock system . one clock is for the cpu and system and the other is for the lcd scanning and interrupt sources. 5.4.1. r oscillator for the cpu and system clock 5.4.1.1. normal case +vdd 5.4.1.2. noisy environment +vdd note: length of the wiring for rosc pin should be minimized because the oscillator frequency varies due to c oupling from other signal lines. 1). 32768hz crystal oscillator or r oscillator (mask option) for lcd scanning and interrupt sources (2khz, lcdl for lcd service, 128hz, 2hz). we suggest enabling 32768hz crystal in strong mode for a few seconds and then switch to weak mode when reset occurs. x32i x32o c1 c2 32768hz 32768hz crystal note: since each crystal has its own characteristics, generalplus recommends users consult the crystal vendor for appropriate c1/c2 values.
gpl10b ? generalplus technology inc. proprietary & confidential 6 may 29, 2014 version: 1.5 +vdd x32i r o scillator r note: length of the wiring for x32i and x32o should be as short as possible. 5.5. stop clock mode the gpl10b supports the power saving mode for those applications needing very low standby current. the user can simply enable the wake-up sources and then stop the cpu clock by writing the stop clock register ($09). the cpu will enter standby and the ram and i/o remain their previous states until wake-up. there are three sources of wake-up in this chip, port ioef wake-up, timer 0 wake-up and 2hz wake-up. after the chip is wakening up, the internal cpu will go to the reset state and the ram and i/o are not affected by the wake-up reset. the standby current of timepiece product typically is less than 8ua @ 3.0v by using this mode and 32768hz clock source in weak mode. for non-timepiece products, 32768hz crystal driver or r oscillator (mask option) generates the 32768h z clock source that also can be turned off to stop the chip operation. the standby current of the gpl10b is less than 1ua @ 3.0v. in this mode, ioef port can be used to wake up the chip. 5.6. timer/counter the gpl10b contains one 12-bit ti mer/counter, tm0. in timer mode, tm0 is reloadable up-counter. when timer overflows from $0fff to $0000, the carry signal will generate the interrupt signal if the corresponding bit is enabled in int enable register ($0d), and the timer will be auto reloaded to the user?s setup value and count up again. if tm0 is be ing specified as a counter, the user may reset the counter by loading 0 into register $14 and $1c. after the counter being activated, the count value can also be read from above registers on-the-fly, the read instruction will not affect the counter's value or reset it. the clock source of the timer/counter are selectable as the following: timer/counter addr. clock source 12 bit timer $0014 $001c cpu clock (t) or t/4 tm0 12 bit counter $0014 $001c t/128, t/256, t/2048 or ext clk mode select register $000b select tm0 timer or counter timer clock selector $001c select t or t/4 5.7. interrupts the gpl10b has six interrupt sources - int0 (interrupt from timer 0), 2khz int, lcdl int (lcd service in share mode, due to lcd registers is shared with the timer/counter), 128hz int, ext int (external interrupt from iocd1), 2hz int. the 2khz int, lcdl int (256 hz in 1/3, 1/4 duty; 128 hz in 1/2 duty), 128hz int, 2hz int, all are derived from 32768hz crystal oscillator by division. 5.8. tone output the gpl10b provides tone output that can directly drive buzzer. it is a full-swing (vdd and vss) signal and its frequency source is the frequency of timer carry divided by 2. the block diagram is shown as below: 2 tone driver aud timer carry tone 5.9. liquid crystal display the gpl10b can directly drive the liquid crystal display (lcd) panel of 1/2 duty, 1/3 duty, and 1/4 duty with 1/2 bias or 1/3 bias. it has 4 commons and 32 segments signal pins. in share mode (timer/counter is used), the lcd is refreshed by lcdl interrupt. the int routine will read the number of common which is under serving, and send the next common's pattern to lcd port ($10 - $13) from ram buffer. if the timer/the counter is not used, hardware mechanism will auto re fresh the lcd after writing option register ($1f).
gpl10b ? generalplus technology inc. proprietary & confidential 7 may 29, 2014 version: 1.5 5.10. output waveform of the lcd driver vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vss vdd vss com0 com1 com2 com3 normal operation 1/2 bias , 1/2 duty lighting format at the initial clear ( reset ) com3 - 0 lcd display on mode lcd segments display on lcd driver output: com0 lcd segments display on lcd driver output: com1 lcd driver output:all the lcd segments display off lcd driver output:all the lcd segments display on
gpl10b ? generalplus technology inc. proprietary & confidential 8 may 29, 2014 version: 1.5 com0 com1 com2 com3 normal operation vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss at the initial clear ( reset ) com3 - 0 lcd display on mode 1/2 bias , 1/3 duty lighting format vdd vss vdd vss lcd segments display on lcd driver output: com0 lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd driver output:com0 and com1 lcd segments display on lcd driver output:com0 and com2 lcd segments display on lcd driver output:com1 and com2 lcd driver output:all the lcd segments display off lcd driver output:all the lcd segments display on
gpl10b ? generalplus technology inc. proprietary & confidential 9 may 29, 2014 version: 1.5 com0 com1 com2 com3 normal operation vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss at the initial clear ( reset ) com3 - 0 lcd display on mode 1/2 bias , 1/4 duty lighting format vdd vss vdd vss lcd driver output:all the lcd segments display off lcd segments display on lcd driver output: com0 lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd driver output: com3 lcd segments display on lcd driver output: com0 and com1 lcd segments display on lcd driver output : com0 and com2 lcd segments display on lcd driver output : com1 and com2 lcd segments display on lcd driver output : com1 and com3
gpl10b ? generalplus technology inc. proprietary & confidential 10 may 29, 2014 version: 1.5 1/3 bias , 1/2 duty lighting format com0 com1 com2 com3 normal operation at the initial clear ( reset ) com3 - 0 lcd display on mode vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd2 vdd1 vdd2 vdd1 vdd2 vdd1 vdd vss vdd vss vss vdd lcd segments display on lcd segments display on lcd driver output: com1 lcd driver output:all the lcd segments display on lcd driver output: com0 lcd driver output:all the lcd segments display off
gpl10b ? generalplus technology inc. proprietary & confidential 11 may 29, 2014 version: 1.5 com0 com1 com2 vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd2 vdd1 vdd2 vdd1 normal operation at the initial clear ( reset ) 1/3 bias , 1/3 duty lighting format com3 - 0 lcd display on mode vdd vss vdd vss com3 lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd segments display on lcd segments display on lcd segments display on lcd driver output: com0 lcd driver output:all the lcd segments display off lcd driver output :com1 and com2 lcd driver output : com0 and com2 lcd driver output : com0 and com1
gpl10b ? generalplus technology inc. proprietary & confidential 12 may 29, 2014 version: 1.5 com0 normal operation vdd vdd2 vdd1 vss at the initial clear ( reset ) 1/3 bias , 1/4 duty lighting format com3 - 0 lcd display on mode vdd vss vdd vss com1 vdd vdd2 vdd1 vss com2 vdd vdd2 vdd1 vss com3 vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd2 vdd1 lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd driver output : com0 and com2 lcd segments display on lcd driver output : com1 and com3 lcd segments display on lcd driver output: com0 lcd segments display on lcd driver output: com3 lcd driver output:all the lcd segments display off
gpl10b ? generalplus technology inc. proprietary & confidential 13 may 29, 2014 version: 1.5 5.11. reset function the gpl10b can be reset by setting the reset pin to ground voltage and its operation starts when this pin is set to power voltage. also an automatic reset function (internal reset function) operates when power is turned on. 5.12. watchdog function the gpl10b provides a watchdog timer. the watchdog timer must be reset when 2hz wake-up by writing $0f; otherwise, it will reset the system. 5.13. mask option the following type mask option is available. 4mhz r oscillator clock resistor: select one of a, b a) internal resistor b) external resistor cpuck frequency: select one of a, b a). 1mhz b). 2mhz ioef0 to ioef5: select one of a, b, c, d (refer to input/output) a). without fixed pull low resistor 200k-ohm, with feedback mos b). with fixed pull low resistor 200k-ohm, without feedback mos c). with fixed pull low resistor 200k,-ohm with feedback mos d). without fixed pull low resistor 200k-ohm, without feedback mos 32768hz clock source: select one of a, b (refer to r oscillator) a). 32768hz crystal oscillator b). r oscillator
gpl10b ? generalplus technology inc. proprietary & confidential 14 may 29, 2014 version: 1.5 6. i/o port configuration 6.1. input ioef port: ioef0 to ioef5 there are four different configurations in ioef port. they are shown as follows: ef port (mask option) : ef port write gnd pl gnd type a input d q 100k 30k ck 30k d q 200k gnd gnd type b input pl 200k 30k gnd ck d q 100k gnd pl gnd type c input ck gnd 30k d q ck type d input pl 6.2. input/output iocd port: iocd0 to iocd3 these four iocd ports can be programmed to be input or output pins independently. these pins also can be used to operate a thermometer by sense m ode. their configurations are shown as below: d q output input 100k gnd input data ck : cd port write cd port the application circuit for sense mode: thermo-resistor iocd1 iocd2 iocd3
gpl10b ? generalplus technology inc. proprietary & confidential 15 may 29, 2014 version: 1.5 7. electrical specifications 7.1. absolute maximum ratings characteristics symbol ratings dc supply voltage v + < 7.0v input voltage range v in -0.5v to v + + 0.5v operating temperature t a -20 to +60 storage temperature t sto -50 to +150 note: stresses beyond those given in the absolute maximum rating t able may cause permanent damage to the device. for normal operati onal conditions, see ac/dc electrical characteristics. 7.2. dc characteristics (vdd = 3.0v, t a = 25 ) limit characteristics symbol min. typ. max. unit condition operating voltage vdd 2.0 - 3.6 v for 2-battery operating current i op - 480 - ua f cpu = 2mhz @ 3.0v, no load standby current i stby - - 1.0 ua vdd = 3.0v, 32768hz off audio output current i aud - -7 - ma vdd = 3.0v, v oh = 2.4v input high level v ih 2.0 - - v vdd = 3.0v input low level v il - - 0.8 v vdd = 3.0v i oh - -3 - ma vdd = 3.0v, v oh = 2.4v iocd output current i ol - 10 - ma vdd =3.0v, v ol = 0.8v 7.3. dc characteristics (vdd = 4.5v, t a = 25 ) limit characteristics symbol min. typ. max. unit condition operating voltage vdd 3.6 - 5.5 v for 3-battery operating current i op - 1.1 - ma f cpu =2mhz @ 4.5v, no load standby current i stby - - 1.0 ua vdd = 4.5v, 32768hz off audio output current i aud - -13 - ma vdd = 4.5v, v oh = 3.6v input high level v ih 3.0 - - v vdd = 4.5v input low level v il - - 0.8 v vdd = 4.5v i oh - -6 - ma vdd = 4.5v, v oh = 3.6v iocd output current i ol - 15 - ma vdd = 4.5v, v ol = 0.9v
gpl10b ? generalplus technology inc. proprietary & confidential 16 may 29, 2014 version: 1.5 7.4. the relationships between the r osc and the f osc 7.4.1. vdd = 3.0v, t a = 25 7.4.2. vdd = 4.5v, t a = 25 7.5. the relationships between the f osc and the vdd 7.6. the relationships between the f cpu and the i op 0 0.5 1 1.5 0123 fcpu(mhz) iop(ma) 4 vdd = 3v vdd = 4.5v 7.7. the relationships between the r osc32k and the f 32k 7.7.1. vdd = 3.0v, t a = 25 0 10 20 30 40 50 60 70 0 5 10 15 20 25 rosc(mohms) fosc(khz) 7.7.2. vdd = 4.5v, t a = 25 0 10 20 30 40 50 60 70 0 5 10 15 20 25 rosc(mohms) fosc(khz)
gpl10b ? generalplus technology inc. proprietary & confidential 17 may 29, 2014 version: 1.5 7.8. the relationships between the f 32k and the vdd 26 28 30 32 34 36 123456 vdd(v) fosc(khz) 7 rosc = 10mohms 7.9. ac characteristics limits characteristics symbol min. typ. max. unit test condition osc frequency f osc - - 4.0 mhz vdd = 2.0v cpu clock f cpu - - 2.0 mhz f cpu = f osc /2 @ 2.0v - 64 - hz 1/2 duty - 85 - hz 1/3 duty frame frequency of the lcd drive f fm1 - 64 - hz 1/4 duty wake-up time t w 6t1 - - sec. - t1 = 1 / (f osc ), tw = 3 x t1, f cpu = f osc /2 sleep system clock cpu clock wake-up t1 tw
gpl10b ? generalplus technology inc. proprietary & confidential 18 may 29, 2014 version: 1.5 8. application circuits 8.1. gpl10b application circuit gpl10b com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 ioef1 ioef2 ioef3 ioef4 ioef5 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 aud x32i x32o iocd0 iocd1 iocd2 iocd3 reset rosc test ioef0 io device lcd i/o inputs common segment reset c5 com 3:0 seg 31:0 audio ckt 100 f seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg23 vdd vdd 0.1 f vdd vss c1 10-22pf* c2 10-22pf* 32768hz 30pf seg8 seg22 note:1. the capacitor values for crystal are for design guidance only. different capacitor values (10-22pf) may be required for differ ent crystal/ resonator used. 2. for crystal : a. quartz crystal characteristics vary according to type, pack age and ma nufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. b. this is the allowable frequency plus and minus deviation over a spe cified temperature range. it is specified in parts per milli on (ppm) referenced to the measured frequency at +25 degrees c. c. temperature range refers to the operating temperature range. do not confuse this with temperature stability. temperature stability depends on the applica tion of the product. if a wide temperat ure stability is required, it should be communicated to the crystal manufacturer.
gpl10b ? generalplus technology inc. proprietary & confidential 19 may 29, 2014 version: 1.5 8.2. audio driver *aud in tone mode buzzer aud gnd
gpl10b ? generalplus technology inc. proprietary & confidential 20 may 29, 2014 version: 1.5 9. package/pad locations 9.1. ordering information product number package type gpl10b - nnnv - c chip form gpl10b - nnnv - ql02x halogen free package - lqfp 64 gpl10b - nnnv - ql02x halogen free package - lqfp 64 lead free note1: code number is assigned for customer. note2: code number (n = a - z or 0 - 9, nn = 00 - 99); version (v = a - z). note3: package form number (x = 1 - 9, serial number).
gpl10b ? generalplus technology inc. proprietary & confidential 21 may 29, 2014 version: 1.5 9.2. package information lqfp 64 outline dimensions dimension in inch symbol min. typ. max. a - - 1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 c1 0.09 - 0.16 d 12.00 d1 10.00 e 12.00 e1 10.00 e 0.50 bsc.
gpl10b ? generalplus technology inc. proprietary & confidential 22 may 29, 2014 version: 1.5 10. disclaimer the information appearing in this public ation is believed to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and patent indemni fication provisions stipulated in the terms of sale only. generalplus makes no warranty, express, statutory implied or by description regarding the information in this pu blication or regarding the freedom of the described chip(s) from patent infringement. further, generalplus makes no warranty of merchantability or fitness for any purpose. generalplus rese rves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other informati on in this publication are current before placing orders. products described herein are intended for use in normal commercial application s. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equip ment, are specifically not recommended without additional processing by generalplus for such app lications. please note that application circuits illustrated in this document are for reference purposes only.
gpl10b ? generalplus technology inc. proprietary & confidential 23 may 29, 2014 version: 1.5 11. revision history date revision # description page may 29, 2014 1.5 1. modify 7.1. 2. modify 8.1 note: adds the description of crystal. 15 18 mar. 12, 2014 1.4 remove p3 note: patent circuitry included. taiwan patent no. 68824. 3 oct. 31, 2012 1.3 1. modify 7.4 relationships between the r osc and the f osc. 2. modify 7.5 relationships between the f osc and the vdd. 16 16 mar. 11, 2010 1.2 1. modify 5.7. interrupts 2. modify 5.10. output waveform of the lcd driver 6 8, 9, 11 dec. 30, 2009 1.1 1. add 7.7 the relationships between the r osc32k and the f 32k . 2. add 7.8 the relationships between the f 32k and the vdd. 16 jul. 10, 2008 1.0 1.modify 7.2 dc characteristics(vdd = 3.0v, ta = 25 ) 2.modify 7.3 dc characteristics(vdd = 4.5v, ta = 25 ) 3. modify 7.4 relationships between the r osc and the f cpu 4. modify 7.5 relationships between the f cpu and the vdd 5. modify 7.6 relationships between the f cpu and the i op 14 14 15 15 15 feb. 14, 2008 0.1 original note: the gpl10b data sheet v1.0 is a c ontinued version of gpl10a5 data sheet v1.4. 21

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